Silicon nanowire field effect transistors (FETs) are attracting significant interest as an evolutionary follow on from a FINFET device structure. With nanowire-based FETs, the nanowires serve as channels that interconnect a source region and a drain region of the device. A gate surrounding the nanowires regulates electron flow through the channels. When the gate fully surrounds a portion of each of the nanowires, this is referred to as a gate-all-around device.
For nanowire FETs (and FINFETs), the wire-to-wire pitch, coupled with the wire diameter, are critical scaling parameters. However, current lithographic limitations are close to the border of what is required to implement these devices in a technology.
Therefore, improved techniques for reducing nanowire dimension and pitch would be desirable.